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features provides analog transmission line interface for t1 and e1 applications provides line driver, jitter attenuator and clock recovery functions fully compliant with at&t 62411 stratum 4, type ii jitter requirements low power consumption b8zs/hdb3/ami encoder/decoder 50 ma transmitter short-circuit current limiting general description the cs61304a combines the complete analog transmit and receive line interface for t1 or e1 applications in a low power, 28-pin device operating from a +5v supply. the cs61304a is a pin-compatible replacement for the lxt304a. the receiver uses a digital delay-locked-loop which is continuously calibrated from a crystal reference to pro- vide excellent stability and jitter tolerance. the cs61304a has a receiver jitter attenuator optimized for t1 cpe applications subject to at&t 62411 and e1 isdn pri applications. the transmitter features inter- nal pulse shaping and a low impedance output stage allowing the use of external resistors for transmitter im- pedance matching. applications primary rate isdn network/termination equipment channel service units ordering information see page 31. may 96 ds156pp2 1 crystal semiconductor corporation p. o. box 17847, austin, texas, 78760 (512) 445-7222 fax:(512) 445-7581 t1/e1 line interface ttip tclk 7 rring rtip tring tgnd 14 control line receiver line driver 15 3 2 6 4 rclk 8 27 lloop (sclk) 25 24 (int) len0 (sdi) len1 (sdo) len2 28 23 (clke) taos 5 mode tpos [tdata] rpos [rdata] rneg [bpv] tneg [tcode] mtip [rcode] dpm [ais] los 12 21 rv+ 22 rgnd 13 19 20 17 11 18 16 mring [pcs] xtalin 9 xtalout 10 aclki 1 ( ) = pin function in host mode [ ] = pin function in extended hardware mode 26 rloop (cs) r e m o t e l o o p b a c k ami, b8zs, hdb3, coder jitter attenuator l o c a l l o o p b a c k clock & data recovery signal quality monitor driver monitor pulse shaper tv+ copyright ? crystal semiconductor corporation 1996 (all rights reserved) cs61304a this document contains information for a new product. crystal semiconductor reserves the right to modify this product without notice. preliminary product information copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cs61304a t1/e1 line interface sep ?05 ds156f1
absolute maximum ratings parameter symbol min max units dc supply (referenced to rgnd=tgnd=0v) rv+ tv+ - - 6.0 (rv+) + 0.3 v v input voltage, any pin (note 1) v in rgnd-0.3 (rv+) + 0.3 v input current, any pin (note 2) i in -10 10 ma ambient operating temperature t a -40 85 c storage temperature t stg -65 150 c warning:operations at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. notes: 1. excluding rtip, rring, which must stay within -6v to (rv+) + 0.3v. 2. transient currents of up to 100 ma will not cause scr latch-up. also ttip, tring, tv+ and tgnd can withstand a continuous current of 100 ma. recommended operating conditions parameter symbol min typ max units dc supply (note 3) rv+, tv+ 4.75 5.0 5.25 v ambient operating temperature t a -40 25 85 c power consumption (notes 4,5) p c - - 350 mw notes: 3. tv+ must not exceed rv+ by more than 0.3v. 4. power consumption while driving line load over operating temperature range. includes ic and load. digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pf capacitive load. 5. assumes 100% ones density, 5.25 v, len2/1/0=1/1/1, a 100 w load and a 1:1.15 transformer. digital characteristics (ta = -40 c to 85 c; tv+, rv+ = 5.0v 5%; gnd = 0v) parameter symbol min typ max units high-level input voltage (notes 6, 7) pins 1-4, 17, 18, 23-28 v ih 2.0 - - v low-level input voltage (notes 6, 7) pins 1-4, 17, 18, 23-28 v il --0.8v high-level output voltage (notes 6, 7, 8) i out = -400 m a pins 6-8, 11, 12, 25 v oh 2.4 - - v low-level output voltage (notes 6, 7, 8) i out = 1.6 ma pins 6-8, 11, 12, 23, 25 v ol --0.4v input leakage current (except pin 5) - - 10 m a low-level input voltage, pin 5 v il --0.2v high-level input voltage, pin 5 v ih (rv+) - 0.2 - - v mid-level input voltage, pin 5 (note 9) v im 2.3 - 2.7 v notes: 6. in extended hardware mode, pins 17 and 18 are digital inputs. in host mode, pin 23 is an open drain output and pin 25 is a tristate digital output. 7. this specification guarantees ttl compatibility (v oh = 2.4v @ i out = -40 m a). 8. output drivers will drive cmos logic levels into a cmos load. 9. as an alternative to supplying a 2.3-to-2.7v input, this pin may be left floating. cs61304a 2 ds156pp2 cs61304a 2 ds156f1
analog specifications (ta = -40 c to 85 c; tv+, rv+ = 5.0v 5%; gnd = 0v) parameter min typ max units transmitter ami output pulse amplitudes (note 10) e1, 75 w (note 11) e1, 120 w (note 12) t1, fcc part 68 (note 13) t1, dsx-1 (note 14) 2.14 2.7 2.7 2.4 2.37 3.0 3.0 3.0 2.6 3.3 3.3 3.6 v v v v e1 zero (space) level (len2/1/0 = 0/0/0) 1:1 transformer and 75 w load 1:1.26 transformer and 120 w load -0.237 -0.3 - - 0.237 0.3 v v load presented to transmitter output (note 10) - 75 - w jitter added by the transmitter (note 15) 10hz - 8khz 8khz - 40khz 10hz - 40khz broad band - - - - - - - - 0.01 0.025 0.025 0.05 ui ui ui ui power in 2khz band about 772khz (notes 10, 16) 12.6 15 17.9 dbm power in 2khz band about 1.544mhz (notes 10, 16) (referenced to power in 2khz band at 772khz) -29 -38 - db positive to negative pulse imbalance (notes 10, 16) t1, dsx-1 e1 amplitude at center of pulse e1 pulse width at 50% of nominal amplitude - -5 -5 0.2 - - 0.5 5 5 db % % e1 transmitter return loss (notes 10, 16, 17) 51 khz to 102 khz 102 khz to 2.048 mhz 2.048 mhz to 3.072 mhz 20 20 20 28 28 24 - - - db db db e1 transmitter short circuit current (notes 10, 18) - - 50 ma rms notes: 10. using a 0.47 m f capacitor in series with the primary of a transformer recommended in the applications section. 11. pulse amplitude measured at the output of a 1:1 transformer across a 75 w load for line length setting len2/1/0 = 0/0/0. 12. pulse amplitude measured at the output of a 1:1.26 transformer across a 120 w load for line length setting len2/1/0 = 0/0/0 or at the output of a 1:1 transformer across a 120 w load for len2/1/0=0/0/1. 13. pulse amplitude measured at the output of a 1:1.15 transformer across a 100 w load for line length setting len2/1/0 = 0/1/0. 14. pulse amplitude measured at the dsx-1 cross-connect across a 100 w load for all line length settings from len2/1/0 = 0/1/1 to len2/1/0 = 1/1/1 using a 1:1.5 transformer. 15. input signal to rtip/rring is jitter free. values will reduce slightly if jitter free clock is input to tclk. 16. not production tested. parameters guaranteed by design and characterization. 17. return loss = 20 log 10 abs((z 1 +z 0 )/(z 1 -z 0 )) where z 1 = impedance of the transmitter, and z 0 = impedance of line load. measured with a repeating 1010 data pattern with len2/1/0 = 0/0/0 and a 1:2 transformer with two 9.4 w series resistors terminated by a 75 w load, or for len2/1/0 = 0/0/1 with a 1:2 transformer and two 15 w series resistors terminated by a 120 w load. 18. measured broadband through a 0.5 w resistor across the secondary of the transmitter transformer during the transmission of an all ones data pattern for len2/1/0 = 0/0/0 or 0/0/1with a 1:2 transformer and the series resistors specified in table a1. cs61304a ds156pp2 3 cs61304a ds156f1 3
analog specifications (ta = -40 c to 85 c; tv+, rv+ = 5.0v 5%; gnd = 0v) parameter min typ max units receiver rtip/rring input impedance - 50k - w sensitivity below dsx (0db = 2.4v) -13.6 500 - - - - db mv data decision threshold t1, dsx-1 (note 19) t1, dsx-1 (note 20) t1, fcc part 68 and e1 (note 21) 60 53 45 65 65 50 70 77 55 % of peak % of peak % of peak allowable consecutive zeros before los 160 175 190 bits receiver input jitter tolerance (note 22) 10khz - 100khz 2khz 10hz and below 0.4 6.0 300 - - - - - - ui ui ui loss of signal threshold (note 23) 0.25 0.30 0.50 v jitter attenuator jitter attenuation curve corner frequency (notes 16, 24) - 3 - hz attenuation at 10khz jitter frequency (notes 16, 24) - 50 - db attenuator input jitter tolerance (notes 16, 24) (before onset of fifo overflow or underflow protection) 138 - - ui notes: 19. for input amplitude of 1.2 v pk to 4.14 v pk . 20. for input amplitude of 0.5 v pk to 1.2 v pk and from 4.14 v pk to rv+. 21. for input amplitude of 1.05 v pk to 3.3 v pk . 22. jitter tolerance increases at lower frequencies. see figure 11. 23. the analog input squelch circuit shall operate when the input signal amplitude above ground on the rtip and rring pins falls within the range of 0.25v to 0.50v. operation of the squelch results in the recovery of zeros. during receive los, the rpos, rneg or rdata outputs are forced low. 24. attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. circuit attenuates jitter at 20 db/decade above the corner frequency. see figure 12. output jitter can increase significantly when more than 138 uis are input to the attenuator. see discussion in the text section. cs61304a 4 ds156pp2 cs61304a 4 ds156f1
e1 switching characteristics (ta = -40 c to 85 c; tv+, rv+ = 5.0v 5%; gnd = 0v; inputs: logic 0 = 0v, logic 1 = rv+; see figures 1, 2, & 3) parameter symbol min typ max units crystal frequency (note 25) f c - 8.192000 - mhz tclk frequency f tclk - 2.048 - mhz tclk pulse width (note 26) t pwh2 150 - 340 ns aclki duty cycle t pwh3 /t pw3 40 - 60 % aclki frequency (note 27) f aclki - 2.048 - mhz rclk duty cycle (note 28) t pwh1 /t pw1 45 50 55 % rise time, all digital outputs (note 29) t r - - 85 ns fall time, all digital outputs (note 29) t f - - 85 ns tpos/tneg (tdata) to tclk falling setup time t su2 25 - - ns tclk falling to tpos/tneg (tdata) hold time t h2 25 - - ns rpos/rneg valid before rclk falling (note 30) t su1 100 194 - ns rdata valid before rclk falling (note 31) t su1 100 194 - ns rpos/rneg valid before rclk rising (note 32) t su1 100 194 - ns rpos/rneg valid after rclk falling (note 30) t h1 100 194 - ns rdata valid after rclk falling (note 31) t h1 100 194 - ns rpos/rneg valid after rclk rising (note 32) t h1 100 194 - ns t1 switching characteristics (ta = -40 c to 85 c; tv+, rv+ = 5.0v 5%; gnd = 0v; inputs: logic 0 = 0v, logic 1 = rv+; see figures 1, 2, & 3) parameter symbol min typ max units crystal frequency (note 25) f c - 6.176000 - mhz tclk frequency f tclk - 1.544 - mhz tclk pulse width (note 26) t pwh2 150 - 500 ns aclki duty cycle t pwh3 /t pw3 40 - 60 % aclki frequency (note 27) f aclki - 1.544 - mhz rclk duty cycle (note 28) t pwh1 /t pw1 45 50 55 % rise time, all digital outputs (note 29) t r - - 85 ns fall time, all digital outputs (note 29) t f - - 85 ns tpos/tneg (tdata) to tclk falling setup time t su2 25 - - ns tclk falling to tpos/tneg (tdata) hold time t h2 25 - - ns rpos/rneg valid before rclk falling (note 30) t su1 150 274 - ns rdata valid before rclk falling (note 31) t su1 150 274 - ns rpos/rneg valid before rclk rising (note 32) t su1 150 274 - ns rpos/rneg valid after rclk falling (note 30) t h1 150 274 - ns rdata valid after rclk falling (note 31) t h1 150 274 - ns rpos/rneg valid after rclk rising (note 32) t h1 150 274 - ns notes: 25. crystal must meet specifications described in cxt6176/cxt8192 data sheet. 26. the transmitted pulse width does not depend on the tclk duty cycle. 27. aclki provided by an external source or tclk. 28. rclk duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached. 29. at max load of 1.6 ma and 50 pf. 30. host mode (clke = 1). 31. extended hardware mode. 32. hardware mode, or host mode (clke = 0). cs61304a ds156pp2 5 cs61304a ds156f1 5
any digital output t r t f 10% 10% 90% 90% figure 1. signal rise and fall characteristics rclk t pw1 t pwl1 t pwh1 host mode (clke = 1) extended hardware mode or hardware host mode (clke = 0) mode or rclk rpos rneg su1 h1 tt rdata bpv figure 2. recovered clock and data switching characteristics switching characteristics (ta = -40 to 85 c; tv+, rv+ = 5%; inputs: logic 0 = 0v, logic 1 = rv+) parameter symbol min typ max units sdi to sclk setup time t dc 50 - - ns sclk to sdi hold time t cdh 50 - - ns sclk low time t cl 240 - - ns sclk high time t ch 240 - - ns sclk rise and fall time t r , t f - - 50 ns cs to sclk setup time t cc 50 - - ns sclk to cs hold time t cch 50 - - ns cs inactive time t cwh 250 - - ns sclk to sdo valid (note 33) t cdv - - 200 ns cs to sdo high z t cdz - 100 - ns input valid to pcs falling setup time t su4 50 - - ns pcs rising to input invalid hold time t h4 50 - - ns pcs active low time t pcsl 250 - - ns notes: 33. output load capacitance = 50pf. cs61304a 6 ds156pp2 cs61304a 6 ds156f1
tclk tpos/tneg t su2 t h2 t pwh2 t pw2 figure 3a. transmit clock and data switching characteristics t dc t cc lsb lsb msb control byte data byte cs sclk sdi t ch t cwh t cch t cdh t cl t cdh figure 4. serial port write timing diagram high z cs sclk sdo clke = 1 t cdz cdv t figure 5. serial port read timing diagram pcs valid input data len0/1/2, taos, rloop, lloop, rcode, tcode t h4 t su4 t pcsl figure 6. extended hardware mode parallel chip select timing diagram aclki t pwh3 t pw3 figure 3b. alternate external clock characteristics cs61304a ds156pp2 7 cs61304a ds156f1 7
theory of operation key enhancements of the cs61304a relative to the lxt304a 12.5% lower power consumption, 50 ma rms transmitter short-circuit current limiting for e1 (per oftel otr-001), optional ami, b8zs, hdb3 encoder/de- coder or external line coding support, receiver ais (unframed all ones) detection, improved receiver loss of signal handling (los set at power-up, reset upon receipt of 3 ones in 32 bit periods with no more than 15 consecutive zeros), transmitter ttip and tring outputs are forced low when tclk is static, introduction to operating modes the cs61304a supports three operating modes which are selected by the level of the mode pin as shown in tables 1 and 2, figure 7, and figures a1-a3 of the applications section. the modes are hardware mode, extended hard- ware mode, and host mode. in hardware and extended hardware modes, discrete pins are used to configure and monitor the device. the ex- tended hardware mode provides a parallel chip select input which latches the control inputs al- lowing individual ics to be configured using a common set of control lines. in the host mode, an external processor monitors and configures the device through a serial interface. there are thir- teen multi-function pins whose functionality is determined by the operating mode. (see table 2). hardware mode extended hardware mode host mode control method control pins control pins with parallel chip select serial interface mode pin level <0.2 v floating or 2.5 v >(rv+)-0.2 v line coding external internal- ami, b8zs, or hdb3 external ais detection no yes no driver performance monitor ye s n o ye s table 1. differences between operating modes mode function pin hardware extended hardware host transmitter 3tpos tdata tpos 4tneg tcode tneg receiver/dpm 6 rneg bpv rneg 7rpos rdata rpos 11 dpm ais dpm 17 mtip rcode mtip 18 mring - mring control 18 - pcs - 23 len0 len0 int 24 len1 len1 sdi 25 len2 len2 sdo 26 rloop rloop cs 27 lloop lloop sclk 2 8 tao s tao s c l k e table 2. pin definitions cs61304a 8 ds156pp2 cs61304a 8 ds156f1
tpos tneg rneg rpos transmit transformer rring receive transformer control cs62180b framer circuit ttip tdata rdata tring line driver ami b8zs, hdb3, coder transmit transformer rloop pcs len0/1/2 lloop taos control hardware mode extended hardware mode host mode control 5 m p serial port rcode tcode clke bpv ais jitter attenuator driver monitor line driver line receiver mtip mring dpm rtip ttip tring t1 or e1 repeater or mux cs61304a cs61304a ttip tpos tneg rneg tring rpos rring rtip rloop len0/1/2 lloop taos control dpm driver monitor line driver line receiver mtip mring cs61304a cs62180b framer circuit jitter attenuator transmit transformer receive transformer receive transformer rring rtip ais detect jitter attenuator line receiver figure 7. overview of operating modes cs61304a ds156pp2 9 cs61304a ds156f1 9
transmitter the transmitter takes digital t1 or e1 input data and drives appropriately shaped bipolar pulses onto a transmission line. the transmit data (tpos & tneg or tdata) is supplied synchronously and sampled on the falling edge of the input clock, tclk. either t1 (dsx-1 or network interface) or e1 ccitt g.703 pulse shapes may be selected. pulse shaping and signal level are controlled by "line length select" inputs as shown in table 3. the output options in table 3 are specified with a 1:1.15 transmitter transformer turns ratio for t1 and a 1:1 turns ratio for e1 without external series resistors. other turns ratios may be used if ap- proriate resistors are placed in series with the ttip and tring pins. table a1 in the applica- tions section lists other combinations which can be used to provide transmitter impedance match- ing. for t1 dsx-1 applications, line lengths from 0 to 655 feet (as measured from the transmitter to the dsx-1 cross connect) may be selected. the five partition arrangement in table 3 meets ansi t1.102 and at&t cb-119 requirements when using #22 abam cable. a typical output pulse is shown in figure 8. these pulse settings can also be used to meet ccitt pulse shape requirements for 1.544 mhz operation. for t1 network interface applications, two addi- tional options are provided. note that the optimal pulse width for part 68 (324 ns) is narrower than the optimal pulse width for dsx-1 (350 ns). the cs61304a automatically adjusts the pulse width based upon the "line length" selection made. the e1 g.703 pulse shape is supported with line length selections len2/1/0 = 0/0/0 and 0/0/1. the pulse width will meet the g.703 pulse shape template shown in figure 9, and specified in ta- ble 4. the cs61304a transmitter provides short-circuit current limiting protection and meets oftel otr-001 short-circuit current limiting require- ments for e1 applications. the cs61304a will detect a static tclk, and will force ttip and tring low to prevent trans- mission when data is not present. when any transmit control pin (taos, len0-2 or lloop) is toggled, the transmitter outputs will require ap- proximately 22 bit periods to stabilize. the transmitter will take longer to stabilize when rloop is selected because the timing circuitry must adjust to the new frequency. 500 1.0 0.5 0 -0.5 0 250 750 1000 normalized amplitude at&t cb 119 specifications pulse shape output time (nanoseconds) ansi t1.102, figure 8. typical pulse shape at dsx-1 cross connect len2 len1 len0 option selected application 011 0-133 ft dsx-1 abam (at&t 600b or 600c) 100 133-266 ft 101 266-399 ft 110 399-533 ft 111 533-655 ft 000 75 w coax e1 ccitt g.703 001 120 w twisted-pair 0 1 0 fcc part 68, opt. a network interface 0 1 1 ansi t1.403 table 3. line length selection cs61304a 10 ds156pp2 cs61304a 10 ds156f1
transmit all ones select the transmitter provides for all ones insertion at the frequency of tclk. transmit all ones is se- lected when taos goes high, and causes continuous ones to be transmitted on the line (ttip and tring). in this mode, the tpos and tneg (or tdata) inputs are ignored. if remote loopback is in effect, any taos request will be ignored. receiver the receiver extracts data and clock from an ami (alternate mark inversion) coded signal and out- puts clock and synchronized data. the receiver is sensitive to signals over the entire range of abam cable lengths and requires no equalization or albo (automatic line build out) circuits. the signal is received on both ends of a center- tapped, center-grounded transformer. the transformer is center tapped on the ic side. the clock and data recovery circuit exceeds the jitter tolerance specifications of publications 43802, 43801, at&t 62411, tr-tsy-000170, and ccitt rec. g.823. a block diagram of the receiver is shown in fig- ure 10. the two leads of the transformer (rtip and rring) have opposite polarity allowing the receiver to treat rtip and rring as unipolar sig- nals. comparators are used to detect pulses on rtip and rring. the comparator thresholds are dynamically established at a percent of the peak level (50% of peak for e1, 65% of peak for t1; with the slicing level selected by len2/1/0 in- puts). the leading edge of an incoming data pulse trig- gers the clock phase selector. the phase selector chooses one of the 13 available phases which the delay line produces for each bit period. the out- 269 ns 244 ns 194 ns 219 ns 488 ns nominal pulse 0 10 50 80 90 100 110 120 -10 -20 percent of nominal peak voltage figure 9. mask of the pulse at the 2048 kbps interface for coaxial cable, 75 w load and transformer specified in application section. for shielded twisted pair, 120 w load and transformer specified in application section. nominal peak voltage of a mark (pulse) 2.37 v 3 v peak voltage of a space (no pulse) 0 0.237 v 0 0.30 v nominal pulse width 244 ns ratio of the amplitudes of positive and negative pulses at the center of the pulse interval 0.95 to 1.05* ratio of the widths of positive and negative pulses at the nominal half amplitude 0.95 to 1.05* * when configured with a 0.47 m f nonpolarized capacitor in series with the tx transformer primary as shown in figures a1, a2 and a3. table 4. ccitt g.703 specifications cs61304a ds156pp2 11 cs61304a ds156f1 11
put from the phase selector feeds the clock and data recovery circuits which generate the recov- ered clock and sample the incoming signal at appropriate intervals to recover the data. data sampling will continue at the periods se- lected by the phase selector until an incoming pulse deviates enough to cause a new phase to be selected for data sampling. the phases of the de- lay line are selected and updated to allow as much as 0.4 ui of jitter from 10 khz to 100 khz, with- out error. the jitter tolerance of the receiver exceeds that shown in figure 11. additionally, this method of clock and data recovery is tolerant of long strings of consecutive zeros. the data sampler will continuously sample data based on its last input until a new pulse arrives to update the clock phase selector. the delay line is continuously calibrated using the crystal oscillator reference clock. the delay line produces 13 phases for each cycle of the ref- erence clock. in effect, the 13 phases are analogous to a 20 mhz clock when the reference clock is 1.544 mhz. this implementation utilizes the benefits of a 20 mhz clock for clock recovery without actually having the clock present to im- pede analog circuit performance. in the hardware mode, data at rpos and rneg should be sampled on the rising edge of rclk, the recovered clock. in the extended hardware mode, data at rdata should be sampled on the falling edge of rclk. in the host mode, clke determines the clock polarity for which output data should be sampled as shown in table 5. 10 1k 10k 1 100 100k 700 .1 1 10 100 .4 28 300 300 peak-to-peak jitter (unit intervals) jitter frequency (hz) at&t 62411 138 minimum performance figure 11. minimum input jitter tolerance of receiver (clock recovery circuit and jitter attenuator) 1 : 2 rtip rring data level slicer edge detector clock phase selector continuously calibrated delay line jitter attenuator rpos rneg rclk data & clock sampling extraction figure 10. receiver block diagram cs61304a 12 ds156pp2 cs61304a 12 ds156f1
loss of signal the receiver will indicate loss of signal after power-up, reset or upon receiving 175 consecu- tive zeros. a digital counter counts received zeros, based on rclk cycles. a zero is received when the rtip and rring inputs are below the input comparator slicing threshold level estab- lished by the peak detector. after the signal is removed for a period of time the data slicing threshold level decays to approximately 300 mv peak . the receiver reports loss of signal by setting the loss of signal pin, los, high. if the serial inter- face is used, the los bit will be set and an interrupt will be issued on int (unless disabled). los will return low (asserting the int pin again in host mode) upon receipt of 3 ones in 32 bit periods with no more than 15 consecutive zeros. note that in the host mode, los is simultane- ously available from both the register and pin 12. rpos/rneg or rdata are forced low during los unless the jitter attenuator is disabled. (see "jitter attenuator") if aclki is present during the los state, aclki is switched into the input of the jitter attenuator, resulting in rclk matching the frequency of aclki. the jitter attenuator buffers any instanta- neous changes in phase between the last recovered clock and the aclki reference clock. this means that rclk will smoothly transition to the new frequency. if aclki is not present, then the crystal oscillator of the jitter attenuator is forced to its center frequency. table 6 shows the status of rclk upon los. jitter attenuator the jitter attenuator reduces wander and jitter in the recovered clock signal. it consists of a fifo, a crystal oscillator, a set of load capacitors for the crystal, and control logic. the jitter attenuator ex- ceeds the jitter attenuation requirements of publications 43802 and rec. g.742. a typical jitter attenuation curve is shown in figure 12. the cs61304a fully meets at&t 62411 jitter attenu- ation requirements. crystal present? aclki present? source of rclk no yes aclki yes no centered crystal yes yes aclki via the jitter attenuator table 6. rclk status at los mode (pin 5) clke (pin 28) data clock clock edge for valid data low (<0.2v) x rpos rneg rclk rclk rising rising high (>(v+) - 0.2v) low rpos rneg sdo rclk rclk sclk rising rising falling high (>(v+) - 0.2v) high rpos rneg sdo rclk rclk sclk falling falling rising middle (2.5v) x rdata rclk falling x = dont care table 5. data output/clock relationship attenuation in db frequency in hz 0 10 20 30 40 50 60 1 10 100 1 k 10 k b) maximum attunuation limit 62411 requirements a) minimum attenuation limit measured performance figure 12. typical jitter transfer function cs61304a ds156pp2 13 cs61304a ds156f1 13
the jitter attenuator works in the following man- ner. the recovered clock and data are input to the fifo with the recovered clock controlling the fifos write pointer. the crystal oscillator con- trols the fifos read pointer which reads data out of the fifo and presents it at rpos and rneg (or rdata). the update rate of the read pointer is analogous to rclk. by changing the load ca- pacitance that the ic presents to the crystal, the oscillation frequency is adjusted to the average frequency of the recovered signal. logic deter- mines the phase relationship between the read and write pointers and decides how to adjust the load capacitance of the crystal. jitter is absorbed in the fifo. the fifo in the jitter attenuator is designed to prevent overflow and underflow. if the jitter am- plitude becomes very large, the read and write pointers may get very close together. should they attempt to cross, the oscillators divide by four circuit adjusts by performing a divide by 3 1/2 or divide by 4 1/2 to prevent data loss from overflow or underflow. the jitter attenuator may be bypassed by pulling xtalin to rv+ through a 1 k w resistor and pro- viding a 1.544 mhz (or 2.048 mhz) clock on aclki. rclk may exhibit quantization jitter of approximately 1/13 uipp and a duty cycle of ap- proximately 30% (70%) when the attenuator is disabled. local loopback local loopback is selected by taking lloop, pin 27, high or by setting the lloop register bit via the serial interface. the local loopback mode takes clock and data presented on tclk, tpos, and tneg (or tdata), sends it through the jitter attenuator and outputs it at rclk, rpos and rneg (or rdata). if the jitter attenuator is disabled, it is bypassed. inputs to the transmitter are still trans- mitted on ttip and tring, unless taos has been selected in which case, ami-coded continu- ous ones are transmitted at the tclk frequency. the receiver rtip and rring inputs are ignored when local loopback is in effect. remote loopback remote loopback is selected by taking rloop, pin 26, high or by setting the rloop register bit via the serial interface. in remote loopback, the recovered clock and data input on rtip and rring are sent through the jitter attenuator and back out on the line via ttip and tring. selecting remote loopback overrides any taos request (see table 7). the recovered incoming signals are also sent to rclk, rpos and rneg (or rdata). a remote loopback oc- curs in response to rloop going high. simultaneous selection of local and remote loop- back modes is not valid (see reset). in the extended hardware mode the transmitted data is looped before the ami/b8zs/hdb3 en- coder/decoder during remote loopback so that the transmitted signal matches the received signal, even in the presence of received bipolar viola- tions. data output on rdata is decoded, however, if rcode is low. rloop input signal tao s input signal source of data for ttip & tring source of clock for ttip & tring 00 tdata tclk 0 1 all 1s tclk 1 x rtip & rring rtip & rring (rclk) notes: 1. x = dont care. the identified all ones select input is ignored when the indicated loopback is in effect. 2. logic 1 indicates that loopback or all ones option is selected. table 7. interaction of rloop with taos cs61304a 14 ds156pp2 cs61304a 14 ds156f1
driver performance monitor to aid in early detection and easy isolation of non-functioning links, the ic is able to monitor transmit drive performance and report when the driver is no longer operational. this feature can be used to monitor either the devices perform- ance or the performance of a neighboring driver. the driver performance monitor indicator is nor- mally low, and goes high upon detecting a driver failure. the driver performance monitor consists of an ac- tivity detector that monitors the transmitted signal when mtip is connected to ttip and mring is connected to tring. dpm will go high if the absolute difference between mtip and mring does not transition above or below a threshold level within a time-out period. in the host mode, dpm is available from both the register and pin 11. whenever more than one line interface ic resides on the same circuit board, the effectiveness of the driver performance monitor can be maximized by having each ic monitor performance of a neigh- boring ic, rather than having it monitor its own performance. alarm indication signal in the extended hardware mode, the receiver sets the output pin ais high when less than 3 zeros are detected out of 2048 bit periods. ais returns low when 4 or more zeros, out of 2048 bits, are detected. line code encoder/decoder in the extended hardware mode, three line codes are available: ami, b8zs and hdb3. the input to the encoder is tdata. the outputs from the decoder are rdata and bpv (bipolar violation strobe). the encoder and decoder are selected using the len2, len1, len0, tcode and rcode pins as shown in table 8. parallel chip select in the extended hardware mode, pcs can be used to gate the digital control inputs: tcode, rcode, len0, len1, len2, rloop, lloop and taos. inputs are accepted on these pins only when pcs is low and will immediately change the operating state of the device. therefore, when cycling pcs to update the operating state, the digital control inputs should be stable for the en- tire pcs low period. the digital control inputs are ignored when pcs is high. power on reset / reset upon power-up, the ic is held in a static state until the supply crosses a threshold of approxi- mately 3 volts. when this threshold is crossed, the device will delay for about 10 ms to allow the power supply to reach operating voltage. after this delay, calibration of the delay lines used in the transmit and receive sections commences. the delay lines can be calibrated only if a reference clock is present. the reference clock for the re- ceiver is provided by the crystal oscillator, or aclki if the oscillator is disabled. the reference clock for the transmitter is provided by tclk. the initial calibration should take less than 20 ms. len 2/1/0 000 010-111 tcode (transmit encoder selection) low hdb3 encoder b8zs encoder high ami encoder rcode (receiver decoder selection) low hdb3 decoder b8zs decoder high ami decoder table 8. encoder/decoder selection cs61304a ds156pp2 15 cs61304a ds156f1 15
in operation, the delay lines are continuously cali- brated, making the performance of the device independent of power supply or temperature vari- ations. the continuous calibration function forgoes any requirement to reset the line interface when in operation. however, a reset function is available which will clear all registers. in the hardware and extended hardware modes, a reset request is made by simultaneously setting both the rloop and lloop pins high for at least 200 ns. reset will initiate on the falling edge of the reset request (falling edge of rloop and lloop). in the host mode, a reset is initiated by simultaneously writing rloop and lloop to the register. in either mode, a reset will set all reg- isters to 0 and force the oscillator to its center frequency before initiating calibration. a reset will also set los high. serial interface in the host mode, pins 23 through 28 serve as a microprocessor/microcontroller interface. one on-board register can be written to via the sdi pin or read from via the sdo pin at the clock rate determined by sclk. through this register, a host controller can be used to control operational characteristics and monitor device status. the se- rial port read/write timing is independent of the system transmit and receive timing. data transfers are initiated by taking the chip se- lect input, cs, low ( cs must initially be high). address and input data bits are clocked in on the rising edge of sclk. the clock edge on which output data is stable and valid is determined by clke as shown in table 5. data transfers are ter- minated by setting cs high. cs may go high no sooner than 50 ns after the rising edge of the sclk cycle corresponding to the last write bit. for a serial data read, cs may go high any time to terminate the output. figure 13 shows the timing relationships for data transfers when clke = 1. when clke = 1, data bit d7 is held until the falling edge of the 16th clock cycle. when clke = 0, data bit d7 is held until the rising edge of the 17th clock cycle. sdo goes high-z after cs goes high or at the end of the hold period of data bit d7. an address/command byte, shown in table 9, pre- cedes a data register. the first bit of the address/command byte determines whether a read or a write is requested. the next six bits contain the address. the line interface responds to address 16 (0010000). the last bit is ignored. cs sclk sdo sdi d6 d5 d4 d3 d2 d1 d0 d7 0 0 d7 d6 d5 d4 d3 d2 d1 d0 address/command byte data input/output 0 0 0 1 0 r/w figure 13. input/output timing lsb, first bit 0 r/ w read/write select; 0 = write, 1 = read 1 add0 lsb of address, must be 0 2 add1 must be 0 3 add2 must be 0 4 add3 must be 0 5 add4 must be 1 6 - reserved - must be 0 msb, last bit 7 x dont care table 9. address/command byte cs61304a 16 ds156pp2 cs61304a 16 ds156f1
the data register, shown in table 10, can be writ- ten to the serial port. data is input on the eight clock cycles immediately following the ad- dress/command byte. bits 0 and 1 are used to clear an interrupt issued from the int pin, which occurs in response to a loss of signal or a problem with the output driver. writing a "1" to either "clear los" or "clear dpm" over the serial interface has three effects: 1) the current interrupt on the serial interface will be cleared. (note that simply reading the register bits will not clear the inter- rupt). 2) output data bits 5, 6 and 7 will be reset as appropriate. 3) future interrupts for the corresponding los or dpm will be prevented from occurring. writing a "0" to either "clear los" or "clear dpm" enables the corresponding interrupt for los or dpm. output data from the serial interface is presented as shown in tables 11 and 12. bits 2, 3 and 4 can be read to verify line length selection. bits 5, 6 and 7 must be decoded. codes 101, 110 and 111 (bits 5, 6 and 7) indicate intermittent loss of sig- nal and/or driver problems. sdo goes to a high impedance state when not in use. sdo and sdi may be tied together in appli- cations where the host processor has a bi-directional i/o port. lsb: first bit in 0 clr los clear loss of signal 1 clr dpm clear driver performance monitor 2 len0 bit 0 - line length select 3 len1 bit 1 - line length select 4 len2 bit 2 - line lenght select 5 rloop remote loopback 6 lloop local loopback msb: last bit in 7 taos transmit all ones select table 10. input data register lsb: first bit in 0 los loss of signal 1 dpm driver performance monitor 2 len0 bit 0 - line length select 3 len1 bit 1 - line length select 4 len2 bit 2 - line lenght select table 11. output data bits 0 - 4 bits status 567 0 0 0 reset has occurred or no program input. 001taos in effect. 0 1 0 lloop in effect. 0 1 1 taos/lloop in effect. 1 0 0 rloop in effect 1 0 1 dpm changed state since last "clear dpm" occured. 1 1 0 los changed state since last "clear los" occured. 1 1 1 los and dpm have changed state since last "clear los" and "clear dpm". table 12. coding for serial output bits 5,6,7 cs61304a ds156pp2 17 cs61304a ds156f1 17
power supply the device operates from a single +5 volt supply. separate pins for transmit and receive supplies provide internal isolation. these pins should be connected externally near the device and decou- pled to their respective grounds. tv+ must not exceed rv+ by more than 0.3v. decoupling and filtering of the power supplies is crucial for the proper operation of the analog cir- cuits in both the transmit and receive paths. a 1.0 m f capacitor should be connected between tv+ and tgnd, and a 0.1 m f capacitor should be con- nected between rv+ and rgnd. use mylar or ceramic capacitors and place them as closely as possible to their respective power supply pins. a 68 m f tantalum capacitor should be added close to the rv+/rgnd supply. wire-wrap bread- boarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors. schematic & layout review service confirm optimum schematic & layout before building your board. for our free review service call applications engineering. call: (512) 445-7222 cs61304a 18 ds156pp2 cs61304a 18 ds156f1
pin descriptions hardware mode top view 22 20 24 19 21 23 25 3 27 2 4 26 28 1 12 14 16 18 13 15 17 8 6 10 5 7 9 11 aclki tclk taos tpos lloop tneg rloop mode len2 rneg len1 rpos len0 rclk rgnd xtalin rv+ xtalout rring dpm rtip los mring ttip mtip tgnd tring tv+ 1 2 3 4 5 6 7 8 9 10 11 12 14 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 aclki taos tclk lloop tpos rloop tneg len2 mode len1 rneg len0 rpos rgnd rclk rv+ xtalin rring xtalout rtip dpm mring los mtip ttip tring tgnd tv+ cs61304a ds156pp2 19 cs61304a ds156f1 19
extended hardware mode 1 2 3 4 5 6 7 8 9 10 11 12 14 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 aclki taos tclk lloop tdata rloop tcode len2 mode len1 bpv len0 rdata rgnd rclk rv+ xtalin rring xtalout rtip ais pcs los rcode ttip tring tgnd tv+ top view 22 20 24 19 21 23 25 3 27 2 4 26 28 1 12 14 16 18 13 15 17 8 6 10 5 7 9 11 aclki tclk taos tdata lloop tcode rloop mode len2 bpv len1 rdata len0 rclk rgnd xtalin rv+ xtalout rring ais rtip los pcs ttip rcode tgnd tring tv+ cs61304a 20 ds156pp2 cs61304a 20 ds156f1
host mode 1 2 3 4 5 6 7 8 9 10 11 12 14 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 aclki clke tclk sclk tpos cs tneg sdo mode sdi rneg int rpos rgnd rclk rv+ xtalin rring xtalout rtip dpm mring los mtip ttip tring tgnd tv+ top view 22 20 24 19 21 23 25 3 27 2 4 26 28 1 12 14 16 18 13 15 17 8 6 10 5 7 9 11 aclki tclk clke tpos sclk tneg cs mode sdo rneg sdi rpos int rclk rgnd xtalin rv+ xtalout rring dpm rtip los mring ttip mtip tgnd tring tv+ cs61304a ds156pp2 21 cs61304a ds156f1 21
power supplies rgnd - ground, pin 22. power supply ground for all subcircuits except the transmit driver; typically 0 volts. rv+ - power supply, pin 21. power supply for all subcircuits except the transmit driver; typically +5 volts. tgnd - ground, transmit driver, pin 14. power supply ground for the transmit driver; typically 0 volts. tv+ - power supply, transmit driver, pin 15. power supply for the transmit driver; typically +5 volts. tv+ must not exceed rv+ by more than 0.3 v. oscillator xtalin, xtalout - crystal connections, pins 9 and 10. a 6.176 mhz (or 8.192 mhz) crystal should be connected across these pins. if a 1.544 mhz (or 2.048 mhz) clock is provided on aclki (pin 1), the jitter attenuator may be disabled by tying xtalin, pin 9 to rv+ through a 1 k w resistor, and floating xtalout, pin 10. overdriving the oscillator with an external clock is not supported. control aclki - alternate external clock input, pin 1. a 1.544 mhz (or 2.048 mhz) clock may be input to aclki, or this pin must be tied to ground. during los, the aclki input signal, if present, is output on rclk through the jitter attenuator. clke - clock edge, pin 28. (host mode) setting clke to logic 1 causes rpos and rneg to be valid on the falling edge of rclk, and sdo to be valid on the rising edge of sclk. conversely, setting clke to logic 0 causes rpos and rneg to be valid on the rising edge of rclk, and sdo to be valid on the falling edge of sclk. cs - chip select, pin 26. (host mode) this pin must transition from high to low to read or write the serial port. int - receive alarm interrupt, pin 23. (host mode) goes low when los or dpm change state to flag the host processor. int is cleared by writing "clear los" or "clear dpm" to the register. int is an open drain output and should be tied to the power supply through a resistor. cs61304a 22 ds156pp2 cs61304a 22 ds156f1
len0, len1, len2 - line length selection, pins 23, 24 and 25. (hardware and extended hardware modes) determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. see table 3 for information on line length selection. also controls the receiver slicing level and the line code in extended hardware mode. lloop - local loopback, pin 27. (hardware and extended hardware modes) setting lloop to a logic 1 routes the transmit clock and data through the jitter attenuator to the receive clock and data pins. tclk and tpos/tneg (or tdata) are still transmitted unless overridden by a taos request. inputs on rtip and rring are ignored. mode - mode select, pin 5. driving the mode pin high puts the line interface in the host mode. in the host mode, a serial control port is used to control the line interface and determine its status. grounding the mode pin puts the line interface in the hardware mode, where configuration and status are controlled by discrete pins. floating the mode pin or driving it to +2.5 v selects the extended hardware mode, where configuration and status are controlled by discrete pins. when floating mode, there should be no external load on the pin. mode defines the status of 13 pins (see table 2). pcs - parallel chip select, pin 18. (extended hardware mode) setting pcs high causes the line interface to ignore the tcode, rcode, len0, len1, len2, rloop, lloop and taos inputs. rcode - receiver decoder select, pin 17. (extended hardware mode) setting rcode low enables b8zs or hdb3 zero substitution in the receiver decoder. setting rcode high enables the ami receiver decoder (see table 8). rloop - remote loopback, pin 26. (hardware and extended hardware modes) setting rloop to a logic 1 causes the recovered clock and data to be sent through the jitter attenuator (if active) and through the driver back to the line. the recovered signal is also sent to rclk and rpos/rneg (or rdata). any taos request is ignored. simultaneously taking rloop and lloop high for at least 200 ns initiates a device reset. sclk - serial clock, pin 27. (host mode) clock used to read or write the serial port registers. sclk can be either high or low when the line interface is selected using the cs pin. sdi - serial data input, pin 24. (host mode) data for the on-chip register. sampled on the rising edge of sclk. sdo - serial data output, pin 25. (host mode) status and control information from the on-chip register. if clke is high sdo is valid on the rising edge of sclk. if clke is low sdo is valid on the falling edge of sclk. this pin goes to a high-impedance state when the serial port is being written to or after bit d7 is output. cs61304a ds156pp2 23 cs61304a ds156f1 23
taos - transmit all ones select, pin 28. (hardware and extended hardware modes) setting taos to a logic 1 causes continuous ones to be transmitted at the frequency determined by tclk. tcode - transmitter encoder select, pin 4. (extended hardware mode) setting tcode low enables b8zs or hdb3 zero substitution in the transmitter encoder. setting tcode high enables the ami transmitter encoder . data rclk - recovered clock, pin 8. the receiver recovered clock generated by the jitter attenuator is output on this pin.when in the loss of signal state aclki (if present) is output on rclk via the jitter attenuator. if aclki is not present during los, rclk is forced to the center frequency of the crystal oscillator. rdata - receive data - pin 7. (extended hardware mode) data recovered from the rtip and rring inputs is output at this pin, after being decoded by the line code decoder. rdata is nrz. rdata is stable and valid on the falling edge of rclk. rpos, rneg - receive positive data, receive negative data, pins 6 and 7. (hardware and host modes) the receiver recovered nrz digital data is output on these pins. in the hardware mode, rpos and rneg are stable and valid on the rising edge of rclk. in the host mode, clke determines the clock edge for which rpos and rneg are stable and valid. see table 5. a positive pulse (with respect to ground) received on the rtip pin generates a logic 1 on rpos, and a positive pulse received on the rring pin generates a logic 1 on rneg. rtip, rring - receive tip, receive ring, pins 19 and 20. the ami receive signal is input to these pins. a center-tapped, center-grounded, 2:1, step-up transformer is required on these inputs, as shown in figure a1 in the applications section. data and clock are recovered and output on rclk and rpos/rneg or rdata. tclk - transmit clock, pin 2. the1.544 mhz (or 2.048 mhz) transmit clock is input on this pin. tpos/tneg or tdata are sampled on the falling edge of tclk. tdata - transmit data, pin 3. (extended hardware mode) transmitter nrz input data which passes through the line code encoder, and is then driven on to the line through ttip and tring. tdata is sampled on the falling edge of tclk. tpos, tneg - transmit positive data, transmit negative data, pins 3 and 4. (hardware and host modes) inputs for clock and data to be transmitted. the signal is driven on to the line through ttip and tring. tpos and tneg are sampled on the falling edge of tclk. a tpos input causes a positive pulse to be transmitted, while a tneg input causes a negative pulse to be transmitted. cs61304a 24 ds156pp2 cs61304a 24 ds156f1
ttip, tring - transmit tip, transmit ring, pins 13 and 16. the ami signal is driven to the line through these pins. the transmitter output is designed to drive a 75 w load between ttip and tring. a transformer is required as shown in table a1. status ais - alarm indication signal, pin 11. (extended hardware mode) ais goes high when unframed all-ones condition (blue alarm) is detected, using the detection criteria of less than three zeros out of 2048 bit periods. bpv- bipolar violation strobe, pin 6. (extended hardware mode) bpv strobes high when a bipolar violation is detected in the received signal. b8zs (or hdb3) zero substitutions are not flagged as bipolar violations if the b8zs (or hdb3) decoder has been enabled. dpm - driver performance monitor, pin 11. (hardware and host modes) dpm goes high if no activity is detected on mtip and mring. los - loss of signal, pin 12. los goes high when 175 consecutive zeros have been received. los returns low when 3 ones are received within 32 bit periods with no more than 15 consecutive zeros. when in the loss of signal state rpos/rneg or rdata are forced low, and aclki (if present) is output on rclk via the jitter attenuator. if aclki is not present during los, rclk is forced to the center frequency of the crystal oscillator. mtip, mring - monitor tip, monitor ring, pins 17 and 18. (hardware and host modes) these pins are normally connected to ttip and tring and monitor the output of a line interface ic. if the int pin in the host mode is used, and the monitor is not used, writing a 1 to the "clear dpm" bit will prevent an interrupt from the driver performance monitor. cs61304a ds156pp2 25 cs61304a ds156f1 25
28 pin plastic dip 1 28 15 14 millimeters inches dim min max min max d b a l c 13.72 14.22 0.540 0.560 36.45 1.02 0.36 0.51 3.94 3.18 0.20 0 15.24 37.21 1.65 0.56 1.02 5.08 3.81 0.38 15 1.435 0.040 0.014 0.020 0.155 0.125 0.600 0.008 0 1.465 0.065 0.022 0.040 0.200 0.150 0.015 15 15.87 0.625 2.41 2.67 0.095 0.105 c ea e1 d b seating plane a b1 e1 a1 l notes: 1. positional tolerance of leads shall be within 0.25mm (0.010") at maximum material condition, in relation to seating plane and each other. 2. dimension ea to center of leads when formed parallel. 3. dimension e1 does not include mold flash. nom 13.97 36.83 1.27 0.46 0.76 4.32 - 0.25 - - 2.54 nom 0.550 1.450 0.050 0.018 0.030 0.170 - - 0.010 - 0.100 a1 b1 e1 e1 ea e e1 d1 d d2/e2 28-pin plcc 28 d2/e2 max min max min millimeters inches dim a 4.57 4.20 0.180 0.165 d/e 12.32 12.57 0.485 0.495 b 0.53 0.33 0.021 0.013 e a a1 b e 2.29 0.090 11.43 11.58 0.450 0.456 9.91 10.92 0.390 0.430 1.19 1.35 0.047 0.053 nom 4.45 12.45 0.41 2.79 11.51 10.41 1.27 nom 0.175 0.490 0.016 0.110 0.453 0.410 0.050 3.04 0.120 d1/e1 a1 cs61304a 26 ds156pp2 cs61304a 26 ds156f1
applications line interface figures a1-a3 show typical t1 and e1 line inter- face application circuits. table a1 shows the external components which are specific to each application. figure a1 illustrates a t1 interface in the host mode. figure a2 illustrates a 120 w e1 interface in the hardware mode. figure a3 illus- trates a 75 w e1 interface in the extended hardware mode. control & monitor frame format encoder/ decoder cs61304a in host mode m p serial port receive line transmit line 28 1 12 11 5 7 6 8 3 4 2 9 10 xtl rv+ + 68 m f rgnd 0.1 m f +5v 21 15 + 1.0 m f tgnd rv+ tv+ clke aclki los dpm mode rpos rneg rclk tpos tneg tclk xtalin xtalout rgnd tgnd 22 14 sclk cs int sdi sdo rtip rring mtip mring tring ttip 27 26 23 24 25 19 20 17 18 16 13 r1 r2 1 3 5 2 6 0.47 m f 2 6 1 5 1:1.15 pe-65388 2ct:1 pe-65351 r3 r4 +5v 100 k w figure a1. t1 host mode configuration frequency mhz crystal xtl cable w r1 and r2 w len2/1/0 transmit transformer r3 and r4 w typical tx return loss db 1.544 (t1) cxt6176 100 200 0/1/1 - 1/1/1 1:1.15 1:2 1:2.3 0 9.4 9.4 0.5 20 28 2.048 (e1) cxt8192 120 240 0/0/0 0/0/0 0/0/1 0/0/1 1:1.26 1:2 1:1 1:2 0 8.7 0 15 0.5 12 0.5 30 75 150 0/0/0 0/0/0 0/0/1 0/0/1 1:1 1:2 1:1 1:2 0 9.4 10 14.3 0.5 24 5 12 table a1. external component values cs61304a ds156pp2 27
control & monitor frame format encoder/ decoder cs61304a in hardware mode line length setting receive line transmit line 28 1 26 27 5 7 6 8 3 4 2 9 10 xtl + 68 m f rgnd 0.1 m f +5v 21 15 + 1.0 m f tgnd rv+ tv+ taos aclki rloop lloop mode rpos rneg rclk tpos tneg tclk xtalin xtalout rgnd tgnd 22 14 len0 len1 len2 rtip rring mtip mring tring ttip 23 24 25 19 20 17 18 16 13 r1 r2 1 3 5 2 6 0.47 m f 2 6 1 5 1:1.26 pe-65389 2ct:1 pe-65351 12 11 los dpm figure a2. 120 w, e1 hardware mode configuration control & monitor frame format encoder/ decoder cs61304a in extended hardware mode line length setting receive line transmit line 17 18 6 28 5 7 8 3 2 9 10 xtl + 68 m f rgnd 0.1 m f +5v 21 15 + 1.0 m f tgnd rv+ tv+ rcode pcs bpv taos mode rdata rclk tdata tclk xtalin xtalout rgnd tgnd 22 14 len0 len1 len2 rtip rring tring ttip 23 24 25 19 20 16 13 r1 r2 1 3 5 2 6 0.47 m f 2 6 3 5 1:1 pe-65389 2ct:1 pe-65351 1 26 aclki rloop 27 12 lloop los 11 ais 4 tcode figure a3. 75 w, e1 extended hardware mode configuration cs61304a 28 ds156pp2
the receiver transformer has a grounded center tap on the ic side. resistors between the rtip and rring pins to ground provide the termina- tion for the receive line. the transmitter transformer matches the 75 w transmitter output impedance to the line imped- ance. figures a1-a3 show a 0.47 m f capacitor in series with the transmit transformer primary. this capacitor is needed to prevent any output stage imbalance from resulting in a dc current through the transformer primary. this current might satu- rate the transformer producing an output offset level shift. transformers recommended transmitter and receiver trans- former specifications are shown in table a2. the transformers in table a3 are recommended for use with the cs61304a. refer to the "telecom transformer selection guide" for detailed sche- matics which show how to connect the line interface ic with a particular transformer. selecting an oscillator crystal specific crystal parameters are required for proper operation of the jitter attenuator. it is rec- ommended that the crystal semiconductor cxt6176 crystal be used for t1 applications and the cxt8192 crystal be used for e1 applications. designing for at&t 62411 for additional information on the requirements of at&t 62411 and the design of an appropriate system synchronizer, please refer to the crystal semiconductor application notes: "at&t 62411 design considerations ? jitter and synchroniza- tion" and "jitter testing procedures for compliance with at&t 62411". transmit side jitter attenuation in some applications it is desirable to attenuate jitter from the signal to be transmitted. a cs61304a in local loopback mode can be used as a jitter attenuator. the inputs to the jitter at- tenuator are tpos, tneg, tclk. the outputs from the jitter attenuator are rpos, rneg and rclk. line protection secondary protection components can be added to provide lightning surge and ac power-cross immunity. refer to the "telecom line protection application note" for detailed information on the different electrical safety standards and specific application circuit recommendations. parameter receiver transmitter turns ratio 1:2 ct 5% 1:1 1.5 % for 75 w e1 1:1.15 5 % for 100 w t1 1:1.26 1.5 % for 120 w e1 primary inductance 600 m h min. @ 772 khz 1.5 mh min. @ 772 khz primary leakage inductance 1.3 m h max. @ 772 khz 0.3 m h max. @ 772 khz secondary leakage inductance 0.4 m h max. @ 772 khz 0.4 m h max. @ 772 khz interwinding capacitance 23 pf max. 18 pf max. et-constant 16 v- m s min. for t1 12 v- m s min. for e1 16 v- m s min. for t1 12 v- m s min. for e1 table a2. transformer specifications cs61304a ds156pp2 29
interfacing the cs61304a with the cs62180b t1 transceiver to interface with the cs62180b, connect the de- vices as shown in figure a4. in this case, the line interface and cs62180b are in host mode con- trolled by a microprocessor serial interface. if the line interface is used in hardware mode, then the line interface rclk output must be inverted be- fore being input to the cs62180b. if the cs61304a is used in extended hardware mode, the rclk output does not have to be inverted be- fore being input to the cs62180b. application turns ratio(s) manufacturer part number package type rx: t1 & e1 1:2ct pulse engineering pe-65351 1.5 kv through-hole, single schott 67129300 bel fuse 0553-0013-hc tx: t1 1:1.15 pulse engineering pe-65388 1.5 kv through-hole, single schott 67129310 bel fuse 0553-0013-rc tx: e1 (75 & 120 w) 1:1.26 1:1 pulse engineering pe-65389 1.5 kv through-hole, single schott 67129320 bel fuse 0553-0013-sc rx &tx: t1 1:2ct 1:1.15 pulse engineering pe-65565 1.5 kv through-hole, dual bel fuse 0553-0013-7j rx &tx: e1 (75 & 120 w) 1:2ct 1:1.26 1:1 pulse engineering pe-65566 1.5 kv through-hole, dual bel fuse 0553-0013-8j rx &tx: t1 1:2ct 1:1.15 pulse engineering pe-65765 1.5 kvsurface-mount, dual bel fuse s553-0013-06 rx &tx: e1 (75 & 120 w) 1:2ct 1:1.26 1:1 pulse engineering pe-65766 1.5 kv surface-mount, dual bel fuse s553-0013-07 rx : t1 & e1 1:2ct pulse engineering pe-65835 3 kv through-hole, single en60950, en41003 approved tx: e1 (75 & 120 w ) 1:1.26 1:1 pulse engineering pe-65839 3 kv through-hole, single en60950, en41003 approved table a3. recommended transformers aclk tclk rclk rpos rneg tpos tneg cs62180b clke sclk int sdo sdi tclk tpos tneg rneg rpos rclk sclk sdo sdi to host controller v+ 100k 1.544 mhz clock signal cs cs v+ 22k mode cs61304a figure a4. interfacing the cs61304a with a cs62180b (host mode) cs61304a 30 ds156pp2
? notes ? cs61304a ds156f1 31 ordering information environmental, manufacturi ng, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. revision history model package temperature CS61304A-IL 28-pin plcc -40 to +85 c model number peak reflow temp msl rating* max floor life CS61304A-IL 225 c 2 365 days revision date changes pp2 may 1996 initial release f1 sep 2005 updated device ordering info. updated legal notice . added msl data.. contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not desi gned, authorized or warranted for use in aircraft systems, military applications, products surgical ly implanted into the body, au tomotive safety or security de- vices, life support products or other critical applic ations. inclusion of cirrus products in such applications is understood to be fully at the customer's risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantab ility and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or cu stomer's customer uses or permits the use of cirrus products in critical applica- tions, customer agrees , by such use, to fully indemnify cirrus, its officers, di rectors, employees, distributors and other agents from any and all liability, including attorneys' fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.
cs61304a 32 ds156f1 - notes -

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